ASIC Physical Design, Sr Staff

Sr. Staff Engineer – ASIC Physical Design

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an experienced ASIC Digital Implementation [Staff/Sr. Staff] Engineer with a deep passion for developing cutting-edge technology. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of Synthesis, Place & Route, and ASIC design flows. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

What You’ll Be Doing:

• Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys’ best in class tools and technologies.
• Work with leading edge designs and teams to drive the industry best PPA for IP designs.
• Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.
• Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
• Work as a liaison between EDAG tool and IP design teams.
• Continuously improve and refine design processes to enhance efficiency and performance.

The Impact You Will Have:

• Drive innovation in high-speed digital IP core and Subsystem development.
• Enhance the efficiency and effectiveness of our design and verification processes.
• Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.
• Ensure the highest quality standards in the design and implementation of our products.
• Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.
• Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

What You’ll Need:

• BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.
• Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
• Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.
• Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
• Good analysis, debugging, and problem-solving skills.
• Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
• Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.
• Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

Who You Are: You are a collaborative and innovative engineer with a strong technical background and a passion for excellence. You thrive in a dynamic environment and enjoy working with global teams to achieve common goals. Your ability to communicate effectively and your commitment to continuous improvement make you an invaluable asset to our team.

The Team You’ll Be A Part Of: You will join the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.