ASIC Physical Design, Staff Engineer

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are a highly driven and detail-oriented engineer with a passion for solving complex problems at the intersection of hardware and software. You thrive in dynamic, fast-paced environments and excel at collaborating with diverse, global teams. Your expertise in ASIC physical design, especially in static timing analysis (STA) for high-performance designs like DDR/LPDDR, HBM, and SOC, sets you apart. You have a proven record of closing challenging designs to meet stringent timing, power, and area requirements. Your background in automation—using Python, Perl, Tcl, and Shell scripting—enables you to streamline processes and enhance the quality and efficiency of RTL2GDS implementation. You communicate clearly and effectively, adept at both presenting your findings and listening to feedback from cross-functional partners. Adaptable and proactive, you take ownership of your projects, continuously seeking innovative solutions to engineering challenges. You are motivated by the opportunity to make a tangible impact on products that power the future of technology, and you value growth, inclusion, and continuous learning.

What You’ll Be Doing:

• Leading static timing analysis (STA) and closure activities for high-performance IPs such as DDR/LPDDR, HBM, and SOC designs.
• Driving timing, power, and area closure for complex ASIC designs, ensuring adherence to stringent requirements.
• Implementing engineering change orders (ECOs) to resolve functional bugs and timing issues in the design flow.
• Enhancing the quality and efficiency of the RTL2GDS implementation process through process optimization and automation.
• Developing and maintaining robust automation scripts using Python, Perl, Tcl, and Shell to streamline repetitive tasks and improve workflow efficiency.
• Collaborating with global cross-functional teams—including design, verification, and product engineering—to ensure seamless project execution.
• Providing technical guidance and mentorship to junior engineers and contributing to team knowledge sharing.

The Impact You Will Have:

• Ensuring world-class timing closure for high-performance IPs, directly contributing to Synopsys’ reputation for quality and innovation.
• Enabling the successful tape-out of advanced semiconductor products by delivering designs that meet or exceed performance and power targets.
• Driving process automation that reduces manual effort, accelerates project schedules, and minimizes errors.
• Supporting the integration of cutting-edge technologies into next-generation chips used in a wide range of applications.
• Facilitating effective communication and collaboration across global teams, enhancing project outcomes and fostering a culture of excellence.
• Contributing to the continuous improvement of physical design methodologies and best practices across the organization.

What You’ll Need:

• 5+yrs of hands-on experience in static timing analysis (STA), particularly in closing timing at chip level.
• In-depth understanding of timing constraints, including handling of asynchronous timing and multiple corner timing closure.
• Experience with industry-standard tools such as PrimeTime (PT), PrimeTime ECO (PTECO), and DMSA.
• Proficiency in scripting languages including Tcl and Python; familiarity with Perl and Shell scripting is a plus.
• Demonstrated ability to implement ECOs for both functional and timing-related issues.
• Familiarity with the RTL2GDS implementation process and a good understanding of physical design flows.

Who You Are:

• Excellent communicator, capable of clearly articulating complex technical information to a variety of audiences.
• Collaborative team player who thrives in a globally distributed, multicultural team environment.
• Analytical thinker with strong problem-solving skills and a keen attention to detail.
• Self-motivated and proactive, taking initiative to drive projects to successful completion.
• Adaptable and open to learning new technologies and methodologies.
• Committed to fostering an inclusive and innovative workplace.

The Team You’ll Be A Part Of: You will join a dynamic and talented physical design team focused on delivering high-performance, low-power ASIC solutions for cutting-edge applications. This team is central to Synopsys’ leadership in semiconductor IP, collaborating closely with global engineering, verification, and product teams. We foster a culture of innovation, continuous improvement, and knowledge sharing, empowering each member to grow and make a significant impact.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.